The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a multi-chip package including at least one memory chip having a Multi-Level Cell (MLC) for storing plural bits of data.
Recently, electronic devices are much smaller and lighter in accordance with the development of a semiconductor industry and the requirement of a user. One of the techniques for making the electronic devices smaller is a multi-chip packaging technique.
The multi-chip packaging technique means a technique for packaging a plurality of semiconductor chips into one package. Here, a method of using the multi-chip package has more advantages than a method of using a plurality of packages respectively having one semiconductor in view of miniaturization, light weight and packaging area.
In addition, a memory device has been rapidly integrated. A memory device having a MLC for storing 2-bit or more data has been developed as one of these integration methods. Here, the MLC has multi-levels. Further, a multi-chip package having a plurality of MLC memory chips has been developed.
On the other hand, in an operation of a common flash memory device, a read time and a program time affects the performance of the memory device. Specially, in the case of the MLC, it is need to separate a read operation and a program operation of each of the bits in a unit cell. Additionally, the program time and the read time are increased accordingly as the number of bits is augmented.
Accordingly, the speed of a MLC flash memory device having a MLC for storing 3-bit or more data is rapidly deteriorated. As a result, the operation of a multi-chip package having at least one MLC memory chip is limited due to data throughput.